1. Description of Technical Field
The present invention relates to a video signal processor, in particular a resolution processor for artificially increasing the resolution of video data.
2. Related Art
At present, most displays for personal computers are multi-scan displays which are suitable for various display modes having resolutions such as 640 (horizontal)xc3x97480 (vertical) dots, 800xc3x97600 dots, 1024xc3x97768 dots, or 1600xc3x971200 dots. In order to obtain a full-screen display of video data with a resolution of 800xc3x97600 dots in a display mode of, for example, 1600xc3x971200 dots, signal processing of doubling the video data both vertically and horizontally is performed to increase the resolution to 1600xc3x971200 dots.
The resolution of a video signal in a television system of the NTSC system is determined when the television system is manufactured. Accordingly, a television receiver which receives video signals in the television system has a resolution corresponding to a video signal. Recently, however, a high-definition television receiver has been produced that enables an image to be displayed with a higher definition than the regulated resolution in the above-mentioned television system by desirably enlarging a video signal in both the vertical and horizontal directions to artificially increase the resolution.
In this manner, the high-definition television receiver and the personal computer change the resolution so as to artificially increase the resolution of a video signal (video data) by enlarging a received video signal by n times both in the vertical and horizontal directions.
FIG. 1 shows a resolution processor which changes the resolution of received video data as described above.
In FIG. 1, the resolution processor comprises a sampling frequency converter 1, a horizontal resolution processor 5, a vertical resolution processor 6, and a resolution processing controller 15.
In the sampling frequency converter 1, a timing detector 3 detects a sampling timing of a video data series D consisting of received video data strings of 8-bit, for example, and supplies a write signal corresponding to the detected timing to a line memory 2. It should be noted that each of the video data corresponds to a pixel of a display unit 14 which is to be described later. The line memory 2 sequentially stores each of the video data in the video data series D in response to a write signal. The line memory 2 further reads out the video data series D stored in the above manner in a receiving order in response to a read signal supplied from the resolution processing controller 15. The line memory 2 supplies the stored data series D as a video data series DC to the horizontal resolution processor 5. The line memory 2 may comprise an FIFO (First In First Out) memory which has a storage capacity of one horizontal scanning line (hereinafter designated as one H-line) of the video data and is capable of writing and reading simultaneously and independently.
The horizontal resolution processor 5 generates a video data series DCH with the increased resolution in the horizontal direction, by performing interpolation processing to the video data series DC sampled at the sampling frequency converter 1. The horizontal resolution processor 5 then supplies the data series DCH to the vertical resolution processor 6.
In the vertical resolution processor 6, a line memory 7 delays the stored video data series DCH by the time corresponding to one H-line to supply the delayed video data series as a delayed video data series DDCH. In this time, the line memory 7 may comprise a FIFO memory having a capacity of storing one H-line of video data in the video data series DCH.
A mixer 9 comprises a first multiplier for multiplying the video data series DCH directly supplied from the horizontal resolution processor 5 by coefficient K1, a second multiplier for multiplying the video data series DDCH by coefficient (1K1), and an adder for adding the outputs of the first and second multipliers to obtain one line of first interpolating video data. The mixer 9 obtains one H-line of first video data series DHV1, by the following operation using the video data series DCH, the delayed video data series DDCH, and a coefficient K1. Then, the mixer 9 supplies the first video data series DHV1, to a frame memory 11.
xe2x80x83DHV1=DCHxc2x7K1+DDCH (1xe2x88x92K1)
A mixer 10 has a similar configuration to that of the mixer 9. The mixer 10 obtains one H-line of second video data series DHV2, by the following operation using the video data series DCH, the delayed video data series DDCH and a coefficient K2,. Then, the mixer 10 supplies the second video data series DHV2 to the frame memory 11.
DHV2=DCHxc2x7K2+DDCH (1xe2x88x92K2)
Wherein the above coefficients K1 and K2 are values depending on the degree of changes in the resolution. The coefficients are generated in the resolution processing controller 15 respectively. In this manner, two outputs are provided from a mixer.
With the above-mentioned configuration, the vertical resolution processor 6 generates two new H-lines of video data series (DHV1, DHV2), by using one H-line of video data series in the video data series DCH and another H-line of video data series just before the former H-line of video data series. This operation produces a video data series having twice as many horizontal scanning lines as the original video data series D, thus increasing the vertical resolution.
The first video data series DHV1 and the second video data series DHV2 are alternately stored into the frame memory 11. From the frame memory 11 the stored video data are sequentially read out and supplied as a high-definition video data series DH to a matrix type display unit 14 such as a plasma display panel. One screen of a display unit 14 is formed with n rows and m columns (nxc2x7m) pixels. In this case, the number of rows, n, indicates the vertical resolution and the number of columns, m, indicates the horizontal resolution. Each of them corresponds to the resolution of the high-definition video data series DH.
As described above, the resolution processor shown in FIG. 1 increases the resolution in the horizontal direction by performing the interpolation processing to the received video data series. And, the resolution processor doubles the resolution in the vertical direction by generating two H-lines of video data from one H-line of video data.
It is also possible to provide three or more mixer and data line pairs for one input. For example, when three pairs of mixer and data line are provided for one input, three output are available for one input, enabling a threefold increase of the resolution in the longitudinal direction (vertical direction).
For instance, in order to increase a video signal with pixels of 640 (horizontal)xc3x97480 (vertical) by three times in both the horizontal and vertical directions, the above configuration requires the line memory 2 to have the capacity for 640 pixels, and the line memory 7 to have a capacity for 1920 pixels. That is, a total of 2560 pixels are required, because the above configuration performs the vertical increasing process after the horizontal increasing process.
In this case, the number of data lines required equals the desired increasing power, namely three data lines and six multipliers in total are necessary in a mixer.
However, the conventional circuit configuration has had a problem in that, changing the resolution requires as many mixers, each having a complicated configuration, as the desired magnification of the vertical resolution.
The present invention has been made in consideration of the above problems, and provides a video signal processor which can freely change a scaling power of the resolution without modifying the circuit configuration.
The present invention is characterized in that a video signal processor comprises a plurality of line memories, each of which stores one horizontal scanning line of video data series, a controller for controlling the plurality of line memories for sequentially storing every horizontal scanning line of video data series in one of the plurality of line memories, and reading the stored data from the plurality of line memories, and an arithmetical unit for receiving two video data series from two of the plurality of line memories and generating one new horizontal scanning line of video data series based on the received video data series. The controller further includes means for selecting a vertical scaling power of the resolution and means for generating a horizontal scanning synchronizing signal having a period depending on the selected scaling power. In the above configuration, the arithmetical unit is triggered by the horizontal scanning synchronizing signal to generate the new horizontal scanning line of video data series.
A video signal processor according to the present invention can increase and decrease the resolution of an image constituted by video data series depending on any value of a scaling power. That is, the vertical resolution of one frame of the image being displayed can be changed to any scaling power.